1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
There are growing demands for higher integration and speed in the manufacturing technology of the integrated circuit field in the electronic industry. In addition, as the circuit size increases according to the improvement in integration, the degree of difficulty in design is also increasing.
An integrated circuit in which a logic circuit and a memory circuit are mounted over the same semiconductor substrate, what is called a composite circuit, has a feature in that the logic circuit and the memory circuit exist over the same substrate. Accordingly, not only the integration efficiency is improved simply because the layout within the short distance is possible, but also the operation speed is increased because a wiring between circuits is short.
However, when a logic circuit and a memory circuit having a capacitive element are mounted over the same semiconductor substrate, it is usually necessary to use a structure, which is not used when the logic circuit is formed, in order to form a capacitive element which is provided in the memory circuit and is used to store the data. For example, in the case of a trench type capacitive element, a technique of forming a deep groove with a depth of several microns or more in a semiconductor substrate and forming a capacitive element in the groove has been reported. However, not only the trench opening size decreases with miniaturization of elements, but also the depth steadily increases in order to ensure the capacitance. As a result, the degree of difficulty in the manufacturing process is increasing extremely.
On the other hand, also in the case of a stacked capacitive element, a fin type or a cylinder type is adopted for the stacked structure in order to realize the desired capacitance. In a so-called COB structure (capacitor over bit line structure) in which a capacitive element is formed over a bit line, it is necessary to increase the height of the capacitor in order to ensure the capacitance of the capacitive element.
Currently, there are various kinds of proposals regarding a semiconductor device in which a wiring layer provided between a lower capacitor wiring and an upper capacitor wiring of a capacitive element is a single layer (for example, see Japanese Unexamined Patent Publication NOS. 2000-003960 and 2005-101647).
Ensuring the height of a capacitive element by using a stacked structure increases the distance between a wiring of a lower capacitor portion and a wiring of an upper capacitor portion.
Accordingly, since the contact height from a first wiring layer to a diffusion layer increases in a logic circuit portion, the level of difficulty is increased in the manufacturing process.
In addition, since the electric resistance of a layer in which the capacitive element is formed increases, that is, since the parasitic resistance also increases, the operation speed is decreased in terms of performance.
Moreover, when designing a logic circuit in the case where a memory circuit and a logic circuit are formed over the same semiconductor substrate as described above, it is necessary to perform the design in which the parasitic resistance and the like are considered, in consideration of the forming of a capacitive element. This means that in the cases where the same logic circuit is designed, a design parameter needs to be changed according to whether or not a capacitive element exists over the same semiconductor substrate, especially according to the difference of wiring resistance or its parasitic capacitance. Accordingly, in spite of the circuits being completely the same, the design work should be performed again only because a logic circuit is formed simultaneously with a capacitive element. In some cases, the operation speed of a circuit may drop or the operation margin may be reduced due to being provided together with a capacitive element and as a result, the circuit may not operate in the end.
As an example of the proposal for reducing the contact height of a logic circuit portion, Japanese Unexamined Patent Publication NO. 2007-201101 may be mentioned first. Japanese Unexamined Patent Publication NO. 2007-201101 discloses that neither a dedicated process nor a dedicated facility for forming a wiring, which is called a plate line for connection between upper electrodes, is needed by connecting upper electrodes of capacitive elements to each other with an upper capacitor wiring formed at the same height as a wiring existing in a logic circuit portion and that the thicknesses of upper and lower layers of the capacitive element can be ensured and the aspect of a contact (logic contact) of the logic circuit portion can be reduced.
Regarding the proposal disclosed in Japanese Unexamined Patent Publication NO. 2007-201101, the contact height may be reduced, but a reduction in the contact height of the logic circuit portion is equivalent to one layer of the wiring height, which is restrictive. In order to increase the capacitance of a capacitive element in this structure, it is necessary to increase the height of the capacitive element. In this case, however, the logic contact height also increases with an increase in capacitance height. As a result, not only the level of difficulty in contact manufacture increases, but also the resistance of the logic contact increases. Moreover, although a copper wiring material containing copper as a main component is preferable as a multi-layered wiring material of the logic circuit portion, a wiring other than the copper wiring material, that is, a tungsten (W) wiring with high resistance is used. In addition, the structure of a wiring layer in which a capacitive element exists is different from the wiring structure of a normal logic circuit due to the existence of the capacitive element. That is, in the layer in which a capacitive element exists, the logic contact height is large and the resistance is also high. As a result, there are needed dedicated design parameters which are not compatible with parameters for design of a normal logic circuit in which all wiring layers are formed of a low-resistance copper material.
In the proposal disclosed in Japanese Unexamined Patent Publication NO. 2004-342787, a first layer wiring is formed in an intermediate portion of a capacitive element in order to reduce the contact height. In this case, the contact height of a logic circuit portion may be reduced similar to Japanese Unexamined Patent Publication NO. 2007-201101. However, even if the method disclosed in Japanese Unexamined Patent Publication NO. 2004-342787 is used, the structure of the logic circuit portion becomes a different structure from the structure in which a capacitive element is not provided because the structure of the logic circuit portion depends on the structure of a capacitive element.
Accordingly, even if the structure disclosed in Japanese Unexamined Patent Publication NO. 2004-342787 is used, it is necessary to use dedicated values as the design parameters of a logic circuit when the logic circuit is provided together with a memory circuit. Moreover, also in the method disclosed in Japanese Unexamined Patent Publication NO. 2004-342787, it is necessary to form a high capacitor by increasing the thickness of an interlayer insulating layer in order to ensure the capacitance of the capacitive element, similar to the method disclosed in Japanese Unexamined Patent Publication NO. 2007-201101. In addition, since not all wirings at the memory circuit side are copper wirings, all multi-layered wirings at the logic circuit side cannot be copper wirings. Also in this case, the level of difficulty when forming a contact increases or the contact resistance increases, similar to Japanese Unexamined Patent Publication NO. 2007-201101. Moreover, in a multi-layered wiring of the latest logic circuit, a low dielectric constant interlayer insulating layer, such as an SiOCH layer, is introduced for at least narrow-pitch local wirings located in a lower layer. Since the low dielectric constant interlayer insulating layer (Low-k layer) has a limitation in thermal resistance, it is not possible to apply a W wiring using CVD-W with high growing temperature, for example. For this reason, Low-k/Cu wirings cannot be formed in all layers of the multi-layered wiring at the logic circuit side. As a result, there are needed dedicated design parameters which are not compatible with parameters for design of a normal logic circuit in which all wiring layers are formed in the Low-k/Cu structure.
Moreover, in the first or third embodiment disclosed in Japanese Unexamined Patent Publication NO. 2004-342787, a structure is shown in which an insulating layer of a silicon oxide layer is formed right above a copper layer of an upper layer wiring or upper electrode. The silicon oxide layer does not have diffusion resistance to the copper layer. Accordingly, in the structure disclosed in Japanese Unexamined Patent Publication NO. 2004-342787, copper (Cu) is diffused into the insulating layer and this deteriorates the reliability of the insulating layer.
Moreover, the silicon oxide layer is mainly formed by oxidation of source gas. Accordingly, when the silicon oxide layer is formed under the conditions in which Cu of the wiring surface is exposed, there are concerns about an increase in wiring resistance caused by oxidation of Cu, a reduction in adhesiveness with the formed silicon oxide layer, a drop in reliability occurring due to those described above, and the like. As described above, in the method disclosed in Japanese Unexamined Patent Publication NO. 2004-342787, there is an advantage in that it is not necessary to provide an etching stopper layer, but it is thought that there is a disadvantage, on the contrary, in that the reliability deteriorates in the structure disclosed in Japanese Unexamined Patent Publication NO. 2004-342787.
Those described up to now may be shown like FIGS. 33A and 33B. As represented by Japanese Unexamined Patent Publication NO. 2004-342787, in the related art, a memory circuit portion 101 has a structure (add-on structure) in which a multi-layered wiring portion 103 is provided over a capacitive element 90. Accordingly, in a logic circuit portion 102, a wiring portion (lift-up wiring portion 104) for lifting up the multi-layered wiring portion 103 according to the height of the capacitive element 90 is needed in order to ensure the capacitance. As a result, there has been a problem that the multi-layered wiring structure becomes thick.